The 6309 is pin compatible with the 6809, and also fully software compatible in it’s default mode. The 6309 and 6809 differ from their “E” versions in the area of the CPU clock. The non-E version uses a crystal in conjunction with an on-chip clock generator to generate the quadrature clock Q and E signals within the CPU – these signals are then presented on the Q and E pins for use by external peripherals. The “E” version requires an external clock generator to feed the Q and E signals into the CPU and to external peripherals.
The pin-outs are identical except for six pins. On the non-E version, the Q and E pins are outputs, and two more pins are used to connect the crystal to the CPU. On the “E” version, the Q and E pins are inputs, and the two pins which are used for the crystal on the non-E chip are now available for two extra signals – TSC (three state control) and LIC (last instruction cycle). If you don’t have a specific need for these two signals, you may ignore them then the chip acts just like a non-E chip. The final two differences are the MRDY and DMA/BREQ pins on the non-E chip are replaced with AVMA and BUSY.
There is almost no information available on the web for the PLCC version of the “E” CPU. However, knowing that the pinouts are identical with the exception of the six pins specified above, that the 6309 and 6809 are hardware compatible and the availability of DIP and PLCC pinouts for the non-E chip and the DIP version of the “E” chip, it’s simple enough to extrapolate the pin assignments for the PLCC “E” chip.
|DIP Pin||PLCC Pin||Function||“E” Function|